Currently, LSIs obtained by integrating semiconductor devices are used for controlling various systems to constitute infrastructures supporting society. Since an operation of a current LSI is based upon conduction of an arithmetic processing according to a program, in most cases, it is inevitable that a program is stored, so that a non-volatile memory which is one of semiconductor memories incorporated into the LSI becomes considerably important as a semiconductor device. When the LSI is used in various applications, programs are required for re-programming to handle the applications. So a rewritable non-volatile memory in which storage information is maintained even when a power source of the LSI is turned off is essential.
As a representative non-volatile memory, a so-called floating gate type memory and a memory having an insulating layer for a charge accumulation layer have been known. Especially, the latter memory where insulating films are stacked and charges are accumulated in interfaces therebetween or traps in the films is not required for formation of another electrically conductive layer that the floating gate type memory requires. Therefore, it is known that the memory can be formed in a CMOS-LSI process with a good consistency. Since both characteristics of retaining charges and rewriting can be achieved, an insulating film obtained by laminating a silicon nitride film and a silicon oxide film is widely used as the charge accumulation layer. A non-volatile memory including such a laminated insulating film is commonly known as MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type memory.
As a representative example of the MONOS type memory, there is a two-transistor cell obtained by connecting a memory transistor and a selection transistor in series. The memory transistor performs injection/discharge of charges over a whole channel region by using a direct tunnel current and an F-N (Folwer-Nordheim) tunnel current generated by a bias applied between the channel and a gate electrode.
However, the above-mentioned MONOS type memory is required to have a sufficient charge retention characteristic while conducting injection/discharge of charges, and that causes various problems. For example, when a laminated insulating film is made thicker for securing the charge retention characteristic sufficiently for a practical use of the MONOS type memory, it becomes difficult to perform writing/erasing of data, so that a time period for writing/erasing exceeds a practical range.
On the other hand, a system in which rewriting of storage information is performed by injecting two electrically different charges (electrons and holes) as hot carriers instead of discharging charges has been proposed in U.S. Pat. No. 6,215,148 (Patent Document 1). The system is for performing a charge injection effectively even in a thick insulating film by injecting hot carriers. According to the system, electrons and holes can be alternately injected at a local place. Therefore, different charge injection states are produced at end portions of a planar type MOS transistor in a channel direction, namely, end portions of a source and a drain, so that they can be read as charge information.
A MONOS type memory using the above-mentioned hot carrier injection system adopts a device structure of a MOS transistor basically, and a gate insulating film is obtained by replacing an ordinary silicon oxide film with a three-layered insulating film made of a silicon oxide film, a silicon nitride film, and a silicon oxide film. As a method for configuring a memory array, it has been proposed that the formation of a source and a drain under a thick element isolation oxide film, and a source and a drain are formed in a line shape in an extending direction of a gate electrode to use them as wires. When focusing on one memory cell in respective memory arrays, in many cases, basic operations of the memory cell are similar, and are explained below.
A plan arrangement and a sectional structure of the above-mentioned MONOS type memory are shown in FIG. 1 and FIG. 2. In figures, a reference numeral 100 denotes a silicon substrate, 200 and 300 denote diffusion layers of a source and a drain, 910 and 940 denote silicon oxide films, 920 denotes a silicon nitride film, and 500 denotes a gate electrode made of a doped polysilicon film.
Writing operation, erasing operation, and reading operation of the above-mentioned MONOS type memory are explained with reference to FIG. 3, FIG. 4, FIG. 5, and FIG. 6.
As shown in FIG. 3, the gate electrode 500 (a word line WL) is applied with 15 V, the diffusion layer 200 (BL1) is applied with 0 V, and the diffusion layer 300 (BL2) is applied with 5 V at a writing time. Electrons accelerated by an electric field of a channel are put in a hot carrier state and are injected into a charge accumulation portion at an end portion of the diffusion layer 300 (BL2). This is known as an avalanche phenomenon and a substrate bias acceleration are used as a method for producing the hot carrier.
As shown in FIG. 4, the gate electrode 500 (word line WL) is applied with −6 V, the diffusion layer 200 (BL1) is applied with 0 V, and the diffusion layer 300 (BL2) is applied with 6 V at an erasing time. Holes are generated at the end portion of the diffusion layer 300 (BL2) by tunneling phenomenon between the bands and they are injected into the charge accumulation portion by acceleration caused by bias between the diffusion layer (BL2) and the substrate.
As shown in FIG. 5, by applying 3 V to the gate electrode 500 (word line WL), applying 1 V to the diffusion layer 200 (BL1), and applying 0 V to the diffusion layer 300 (BL2), an amount of channel current flowing in a direction of the arrow shown in FIG. 5 is read as accumulated charge information at a reading time. That is, a threshold is high when electrons have been injected at an end portion of the diffusion layer 300 (BL2) so that no channel current flows, but the threshold is low when holes have been injected at the end portion so that much channel current flows.
In the case of the above-mentioned MONOS type memory, the threshold is largely influenced by charges injected at an end portion of a diffusion layer serving as a source side at the reading time, but does not depend on a charge state of an end portion of the diffusion layer serving as a drain side so much. Therefore, one memory cell can be used as 2 bits by using the above-mentioned diffusion layer 200 and the diffusion layer 300 in an interchanging manner. FIG. 6 shows that that reading operation is performed by injecting electrons and holes into the diffusion layer 200 (BL1) and the diffusion layer 300 (BL2), respectively. Here, it is shown that the holes (shown by a white circle) and the electrons (shown by a black circle) are accumulated in the diffusion layer 200 (BL1) and in the diffusion layer 300 (BL2), respectively.
U.S. Pat. No. 5,969,383 (Patent Document 2) and U.S. Pat. No. 6,477,084 (Patent Document 3) disclose a memory cell called “split gate structure” as another example of the MONOS type memory. In the memory cell, two MOS transistors (a selection transistor and a memory transistor), basically each based upon an n-channel type MOS transistor, are coupled to each other in a state that the memory transistor is stacked in a vertical manner beside the selection transistor. An equivalent circuit of the memory cell is shown in FIG. 9. FIG. 7 and FIG. 8 are a plan view and a sectional view of the memory cell corresponding to the circuit shown in FIG. 9. In figures, reference numerals 210 and 310 denote n− diffusion layers, 900 denotes a gate insulating film made of a silicon oxide film, 500 denotes a selector gate, 550 denotes a memory gate, and 960 denotes a side wall spacer made of a silicon oxide film.
Here, an operating method for the memory cell will be first explained, but a manufacturing method for the memory cell and the like will be later explained in detail by using embodiments thereof. A circuit configuration of a memory array using the memory cells is shown in FIG. 10. Respective gate electrodes (selector gate 500 and a memory gate 550) of the selection transistor and the memory transistor configure word lines indicated by SGL and MGL. The diffusion layer 300 of the selection transistor configures a bit line BL, and the diffusion layer 200 of the memory transistor configures a source line SL.
Representative writing/erasing operations of the above-mentioned memory cell are shown in FIG. 11 and FIG. 12. A gate insulating film 950 of the memory gate 550 has a MONOS structure that a silicon nitride film is interposed between two layers of silicon oxide films. A gate insulating film 900 of the selector gate 500 comprises a silicon oxide film. The diffusion layers 200 and 300 are formed by ion implantation of impurities using the selector gate 500 and the memory gate 550 as masks, respectively. As basic operations of the memory cell, there are four states of (1) writing, (2) erasing, (3) retaining, and (4) reading. However, the designations of the four states are used as typical ones, and the “writing” and the “erasing” can be called in an inversed manner. Although the operations are explained based on typical ones, it is considered that there are various different operations. Here, a memory cell configured by two n-channel type MOS transistors (a selection transistor and a memory transistor) will be described, but a memory cell configured by two p-channel type MOS transistors can also be similarly explained in principle.
(1) The writing operation is shown in FIG. 11. A positive potential is applied to the diffusion layer 200 on the memory gate 550 side and the same ground potential as that of a silicon substrate 100 is applied to the diffusion layer 300 on the selector gate 500 side. By applying a high gate overdrive voltage to the memory gate 550 with respect to the silicon substrate 100, a channel under the memory gate 550 is put in ON state. In this case, by setting the potential of the selector gate 500 to be higher than the threshold by about 0.1 V to 0.2 V, switching to ON state is conducted. At this time, since the most intense electric field occurs near a boundary between two gate electrodes (500, 550), many hot electrons are generated to be injected into a gate insulating film 950 on the memory gate 550 side. A reference numeral 800 shows generation of carries by impact ionization. The electrons and holes are shown by a white circle and a hatching black circle, respectively. This phenomenon is also known as source side injection (SSI).
A feature of a hot electron injection according to this system is that the injection is intensively performed on the end portion of the memory gate 550 on the selector gate 500 side because the electric field concentrates near the boundary between the selector gate 500 and the memory gate 550. In a floating gate type memory, a charge retention layer is made of an electrically conductive film. By contrast, in the insulating film type memory, electrons are accumulated in an insulating film, therefore, electrons are retained at an extremely small region.
(2) The erasing operation is shown in FIG. 12. By applying a negative potential to the memory gate 550 and applying a positive potential to the diffusion layer 200 on the memory gate 550 side, intense inversion occurs in an overlapping region of the memory gate 550 at the end portion of the diffusion layer 200 and the diffusion layer 200, so that tunnel phenomenon between the bands is caused, and hot holes 810 are produced. In the memory cell, the holes generated are accelerated toward the channel direction, and are attracted by bias of the memory gate 550 to be injected into the gate insulating film 950, so that the erasing operation is performed. It is shown that the holes generated produce secondary electron-hole pairs 820 in FIG. 12. These carriers are also injected into the gate insulating film 950. That is, the threshold of the memory gate 550 which has been increased due to charge of electrons is pulled down by charges of the holes injected.
(3) at the charge retaining time, the charge is retained as charge of carriers injected into the gate insulating film 950. Since movement of the carriers in the gate insulating film 950 is extremely small and slow, the charge is stably retained even if a voltage is not applied to the electrode.
(4) at the reading time, by applying a positive potential to the diffusion layer 300 on the selector gate 500 side and applying a positive potential to the selector gate 500, a channel under the selector gate 500 is turned ON. Here, by application of a proper memory gate potential (that is, an intermediate potential between the threshold in the writing state and the threshold in the erasing state) in which a difference between the thresholds of the memory gate 550 given by the writing/the erasing states can be discriminated, charge information retained is read as a current.
As described above, the feature of the carrier injection using hot carriers lies in that the injection can be performed efficiently even if an insulating film between the silicon substrate and the silicon nitride film which is the charge retention layer is thick. This is because energy of hot carriers is approximately equal to a barrier potential of the insulating film measured from a silicon band. However, injection of carriers in high energy state from the substrate side via the insulating film produces many defects on an interface between the channel of the substrate and the insulating film. So carriers are trapped in the defects at a reading time, so that failures at the reading time such as degradation or fluctuation of the threshold are caused.
Especially, since band offset of the silicon oxide film serving as the gate insulating film 900 directly existing on the channel with respect to silicon is higher to holes than to electrons, a hot hole injection requires higher energy holes than an electron energy in the hole electron injection. Therefore, when the hot hole injection is adopted, damage imparted to an interface between the channel and the insulating film becomes more severe than that in a case that the hot electron injection is adopted.
In such a hot carrier injection system such as a source side injection (SSI) and a band-to-band tunnel hot hole injection (BTBTHH injection), a carrier injection is performed at a local place, so that carriers injected into the charge accumulation layer (silicon nitride film) gradually diffuse over time, which causes fluctuation in the threshold and degradation of the charge retention characteristic.
These problems are caused by degradation of a channel interface due to an injection of holes from the substrate by using hot carriers. It is also thought that the problems are caused by a local injection of holes from a high electrical field position. Therefore, when the injection of holes is performed from the substrate, holes are required to be injected non-locally without using hot carriers while a film thickness assuring sufficient charge retention characteristic is ensured.
As a method of solving the problem, an injection of holes without using hot carriers is disclosed in 2004 International Reliability Symposium Proc. pp. 527-530 by E. Lusky et al. (Non-Patent Document 1). In a conventional laminated gate insulating film structure using a silicon oxide film as a barrier layer, since a silicon oxide film formed between a silicon nitride film and a silicon substrate is thick, it is impossible to perform a tunnel injection of holes from a channel. Therefore, in Non-Patented Document 1, a laminated film made of a extremely thin silicon oxide film, an extremely thin silicon nitride film, and an extremely thin silicon oxide film is formed instead of the silicon oxide film, so that such holes can tunnel easily from the substrate side at an application of electric field.
However, since it is necessary to use the substrate side as a channel at a reading time, it is necessary to form the silicon oxide film thickly in order to maintain channel characteristic and suppress change in the threshold due to disturbance. In addition, since charges are moved through the barrier film at an injection time of holes, the holes pass through a channel interface, whereby degradation of an interface characteristic cannot be avoided. Further, it is thought that carries are trapped in the silicon nitride film in the laminated film made of the extremely thin silicon oxide film, the extremely thin silicon nitride film, and the extremely thin silicon oxide film during writing/erasing operations, so that fluctuation in the threshold due to release of trapped carriers can not be avoided.
As a non-local hole injection system which does not cause degradation of an interface, a non-local hole injection from a gate electrode is thought. However, since a valence band offset between silicon oxide and silicon is as high as 4.7 eV, it is difficult to conduct a hole injection from the gate electrode when an insulating film positioned under the gate electrode is a thick silicon oxide film.
As mentioned in Japanese Patent Application Laid-open Publication No. 2004-303918 (Patent Document 4), a system that holes are injected from a gate electrode side by applying a positive voltage to the gate electrode, in which a gate insulating film has a laminated film structure in which a silicon oxide film, a silicon nitride film, and a silicon oxynitride (SiON) film are formed successively from a substrate side, has been proposed.
A sectional view of the memory cell is shown in FIG. 16. A reference numeral 200 denotes a source, 300 denotes a drain, 901 denotes a silicon oxide film, 920 denotes a silicon nitride film, 930 denotes a silicon oxynitride film, and 500 denotes a gate electrode. A charge accumulation layer is the silicon nitride film 920. Electrons are hot-electron-injected from a substrate at a writing time, and holes are injected from the gate electrode at an erasing time. According to this system, by adopting the insulating film on the gate electrode 500 side made of silicon oxynitride (SiON) having a band gap smaller than that of silicon oxide and having a low barrier wall to holes, it is made possible to cause holes to F-N (Folwer-Nordheim)-tunnel by a small electric field at an erasing time.
Incidentally, as shown in FIG. 15, it is generally thought that an interface state between a polysilicon film configuring the gate electrode 500 and the silicon oxynitride film 930 is made excellent by interposing a thin silicon oxide film 940 with a thickness of about 1 nm between an interface of the gate electrode 500 and the silicon oxide nitride film 930. In this case, since the holes can directly tunnel from the gate electrode 500 through the thin silicon oxide film 940 with a thickness of about 1 nm, the thin silicon oxide film 940 is not a main factor for determining a transmittance at a hole injecting time. Main factors for determining an injection efficiency of the holes are a film thickness of the silicon oxynitride film 930 and a band offset to the holes thereof.